Search - shift register in VHDL

[Windows Develop] 移位寄存器

Description: 移位寄存器，VHDL编写，具有很高的参考价值~-a shift register written in VHDL, which has very high reference value.
Platform: | Size: 1024 | Author: 许 | Hits:

Description: 数字通信系统的设计及其性能和所传输的数字信号的统计特性有关。所谓加扰技术，就是不增加多余度而扰乱信号，改变数字信号的统计特性，使其近似于白噪声统计特性的一种技术。这种技术的基础是建立在反馈移位寄存器序列（伪随机序列）理论之上的。解扰是加扰的逆过程，恢复原始的数字信号。如果数字信号具有周期性，则信号频谱为离散的谱线，由于电路的非线性，在多路通信系统中，这些谱线对相邻信道的信号造成串扰。而短周期信号经过扰码器后，周期序列变长，谱线频率变低，产生的非线性分量落入相邻信道之外，因此干扰减小。在有些数字通信设备中，从码元“0”和“1”的交变点提取定时信息，若传输的数字信号中经常出现长的“1”或“0”游程，将影响位同步的建立和保持。而扰码器输出的周期序列有足够多的“0”、“1”交变点，能够保证同步定时信号的提取。 -digital communication system design and performance and the transmission of digital signals on the statistical characteristics. The so-called scrambling technology is not to increase the degree to disrupt redundant signal, digital signal change the statistical properties it is similar to white noise statistical characteristics of a technology. This technology is based on feedback shift register sequences (pseudo-random sequence) of the above theory. Decryption is the reverse of the scrambling process, the restoration of the original digital signal. If the digital signal is cyclical, the signal spectrum of discrete lines, as the nonlinear circuit, in multi-channel communication system, these lines of the adjacent channel signal causing crosstalk. And the short-cycle signal after scrambling
Platform: | Size: 113664 | Author: 葛岭泉 | Hits:

[VHDL-FPGA-Verilog] spi

Description: VHDL实现SPI功能源代码 -- The SPI bus is a 3 wire bus that in effect links a serial shift -- register between the "master" and the "slave". Typically both the -- master and slave have an 8 bit shift register so the combined -- register is 16 bits. When an SPI transfer takes place, the master and -- slave shift their shift registers 8 bits and thus exchange their 8 -- bit register values.-SPI realize the functional VHDL source code The SPI bus is a 3 wire bus that in effect links a serial shift register between the
Platform: | Size: 65536 | Author: 阿飞 | Hits:

[Other] shift8

Description: 8 位移位寄存器 VHDL程序 VHDL程序 VHDL程序-8-bit shift register VHDL procedures VHDL procedures VHDL procedures
Platform: | Size: 197632 | Author: 周辉 | Hits:

[VHDL-FPGA-Verilog] LFSR

Description: 自动生成线形反馈移位寄存器的各种HDL源代码和原理图的工具-Automatic generation of linear feedback shift register of a variety of HDL source code and schematic tools
Platform: | Size: 162816 | Author: zx | Hits:

[VHDL-FPGA-Verilog] fcsr

Description: 伪随机序列产生器－代进位反馈移位寄存器，verilog hdl 原代码。-Pseudo-random sequence generator- on behalf of binary feedback shift register, verilog hdl original code.
Platform: | Size: 1024 | Author: 李辛 | Hits:

[VHDL-FPGA-Verilog] shifter

Description: 8位双向移位寄存器: 实现串行数据与并行数据的转换,移位寄存数据功能的-8-bit bi-directional shift register: the realization of serial data and parallel data conversion, data storage function of displacement
Platform: | Size: 45056 | Author: 罗子 | Hits:

[VHDL-FPGA-Verilog] R

Description: 双向移位寄存器的原理设计程序，对于初学者将会有很大帮助，尤其在设计功能比较复杂的FPGA时，有些问题其实用这个就很简单-The principle of bi-directional shift register the design process, for beginners there will be a great help, especially in the design features of the FPGA more complex, there are some problems with this very simple
Platform: | Size: 2048 | Author: lijq | Hits:

[VHDL-FPGA-Verilog] shift

Description: Simple shift register with testbench in vhdl
Platform: | Size: 1024 | Author: Tukan | Hits:

[VHDL-FPGA-Verilog] mux_reg

Description: VHDL code for a multiplexer and a parallel/serial in parallel/serial out shift register
Platform: | Size: 1024 | Author: Davood | Hits:

[GIS program] shiftregister_32

Description: 长度为8的32bit串入并出移位寄存器,它的功能就是对32bit的并行信号作串行输入，并行输出处理-Length of 8 for 32bit serial in parallel out shift register
Platform: | Size: 1024 | Author: 林伟 | Hits:

[VHDL-FPGA-Verilog] left_shift_register

Description: 用ＥＤＡ实现的一个带有同步并行预置功能的８位左移移位寄存器-With the EDA to achieve a preset function in parallel with synchronous 8-bit left shift register
Platform: | Size: 147456 | Author: 哈哈 | Hits:

[Windows Develop] LFSR

Description: verilog实现的8阶伪随机序列发生器，文件包含了三种主要模块：控制模块，ROM模块，线性反馈移位寄存器（LFSR）模块。已经通过modelsim仿真验证。-verilog to achieve 8-order pseudo-random sequence generator, the file contains three main modules: control module, ROM modules, a linear feedback shift register (LFSR) module. Has passed modelsim simulation.
Platform: | Size: 870400 | Author: 风影 | Hits:

[VHDL-FPGA-Verilog] vhdl_pgms

Description: Program for Counter, mealy machine, moore machine, ones counter, seven segment with zero blanking and shift register in VHDL.
Platform: | Size: 3072 | Author: Sivraj P | Hits:

[VHDL-FPGA-Verilog] sipo

Description: Serial In Parallel Out Shift Register in VHDL in Modelsim
Platform: | Size: 1024 | Author: Sivraj P | Hits:

[VHDL-FPGA-Verilog] SHFRT4_1

Description: 四位串入并出移位寄存器,实现串并转换,已通过时序验证-Four series in and out of shift register, to achieve string and conversion, has passed the timing verification
Platform: | Size: 200704 | Author: 寒星 | Hits:

[VHDL-FPGA-Verilog] reexercise3

Description: shift register in vhdl
Platform: | Size: 1024 | Author: cdac | Hits:

[VHDL-FPGA-Verilog] shift16

Description: The data in the shift register in shift pulses can move or by bit right next moves left, data can be parallel input, parallel output, also can serial input, serial output, still can parallel input, output, serial input, serial, parallel output is flexible, use also is very wide.
Platform: | Size: 277504 | Author: 张凯 | Hits:

[VHDL-FPGA-Verilog] shift

Description: VHDL写的移位寄存器，可以应付老师的检查，能下载到板子上跑-Shift register can be written in VHDL the teacher checks payable can be downloaded to the board ran
Platform: | Size: 2048 | Author: 胡恒 | Hits:

[VHDL-FPGA-Verilog] shift_reg_control

Description: vivado project for shift register in vhdl
Platform: | Size: 89088 | Author: sandeepthi | Hits:

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[Windows Develop] 移位寄存器

[Other] SC-DSC

[VHDL-FPGA-Verilog] spi

[Other] shift8

[VHDL-FPGA-Verilog] LFSR

[VHDL-FPGA-Verilog] fcsr

[VHDL-FPGA-Verilog] shifter

[VHDL-FPGA-Verilog] R

[VHDL-FPGA-Verilog] shift

[VHDL-FPGA-Verilog] mux_reg

[GIS program] shiftregister_32

[VHDL-FPGA-Verilog] left_shift_register

[Windows Develop] LFSR

[VHDL-FPGA-Verilog] vhdl_pgms

[VHDL-FPGA-Verilog] sipo

[VHDL-FPGA-Verilog] SHFRT4_1

[VHDL-FPGA-Verilog] reexercise3

[VHDL-FPGA-Verilog] shift16

[VHDL-FPGA-Verilog] shift

[VHDL-FPGA-Verilog] shift_reg_control

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